/******************************************************************
 *  MRRM's testbench - register file                              *
 *                                                                *
 *  This file is part of the MRRM project                         *
 *  <http://mrrm.googlecode.com/>                                 *
 *                                                                *
 *  Author(s):                                                    *
 *    -  Wu Jinkai                                                *
 *                                                                *
 ******************************************************************
 *                                                                *
 *  Copyright (C) 2010 AUTHORS                                    *
 *                                                                *
 *  This source file may be used and distributed without          *
 *  restriction provided that this copyright statement is not     *
 *  removed from the file and that any derivative work contains   *
 *  the original copyright notice and the associated disclaimer.  *
 *                                                                *
 *  MRRM is free software: you can redistribute it and/or modify  *
 *  it under the terms of the GNU General Public License as       *
 *  published by the Free Software Foundation, either version 3   *
 *  of the License, or (at your option) any later version.        *
 *                                                                *
 *  MRRM is distributed in the hope that it will be useful, but   *
 *  WITHOUT ANY WARRANTY; without even the implied warranty of    *
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the  *
 *  GNU General Public License for more details.                  *
 *                                                                *
 *  You should have received a copy of the GNU General Public     *
 *  License along with MRRM. If not, see                          *
 *  <http://www.gnu.org/licenses/>.                               *
 *                                                                *
 ******************************************************************/

`include "global.v"

module mrrm_test_rf;

  parameter dw = `OPERAND_WIDTH;
  parameter aw = `REGFILE_ADDR_WIDTH;
  
  // Clock and reset
  reg clk;
  reg rst;
  // Write interface
  reg [aw-1:0] addrx;
  reg [aw-1:0] addry;
  reg [dw-1:0] datax;
  reg [dw-1:0] datay;
  reg wrx;
  reg wry;
  // Read interface
  reg [aw-1:0] addra;
  reg [aw-1:0] addrb;
  reg [aw-1:0] addrc;
  // Internal wires and regs
  wire [dw-1:0] dataa;
  wire [dw-1:0] datab;
  wire [dw-1:0] datac;

mrrm_rf t_mrrm_rf(
  .clk(clk), .rst(rst),
  .addrx(addrx), .addry(addry), 
  .datax(datax), .datay(datay), 
  .wrx(wrx), .wry(wry),
 	.addra(addra), .addrb(addrb), .addrc(addrc), 
 	.dataa(dataa), .datab(datab), .datac(datac)
  );

initial
  begin
    // Initial
    clk = 0;
    rst = ~`RST_VALUE;
    addrx = 0;
    addry = 0;
    datax = 0;
    datay = 0;
    wrx = 0;
    wry = 0;
    addra = 0;
    addrb = 0;
    addrc = 0;
    
    
    // Write & Read test
    #90 wrx = 1;
    begin: writeX
      integer i;
      for(i = 0; i <= 31; i = i + 1)
      begin
        #20 addrx = i;
        datax = i;
      end
    end
    
    // X & A
    begin: readXA
      integer i;
      for(i = 0; i <= 31; i = i + 1)
        #20 addra = i;
    end
    
    // X & B
    begin: readXB
      integer i;
      for(i = 0; i <= 31; i = i + 1)
        #20 addrb = i;
    end
    
    // X & C
    begin: readXC
      integer i;
      for(i = 0; i <= 31; i = i + 1)
        #20 addrc = i;
    end
    
    // Y & A
    #100 wrx = 0;
    wry = 1;
    addra = 0;
    addrb = 0;
    addrc = 0;
    begin: writeY
      integer i;
      for(i = 0; i <= 31; i = i + 1)
      begin
        #20 addry = i;
        datay = i + 32;
      end
    end
    
    begin: readYA
      integer i;
      for(i = 0; i <= 31; i = i + 1)
        #20 addra = i;
    end
    
    // Y & B
    begin: readYB
      integer i;
      for(i = 0; i <= 31; i = i + 1)
        #20 addrb = i;
    end
    
    // Y & C
    begin: readYC
      integer i;
      for(i = 0; i <= 31; i = i + 1)
        #20 addrc = i;
    end
    
    
    // RST test
    #90 wrx = 0;
    wry = 0;
    rst = `RST_VALUE;
    
    
    // Competition test 
    #10 rst = ~`RST_VALUE;
    datax = 32'b00010010001101000000101111001101; //12340bcd
    datay = 32'b00001011110011010001001000110100; //0bcd1234
    addra = 0;
    addrb = 0;
    addrc = 0;
    addrx = 0;
    addry = 0;
    #10 wrx = 1;
    #5 wry = 1;

    
    #100 $stop;
  end

initial
  begin
    $monitor("Time@%d, dataa=%h, datab=%h, datac=%h",
      $time, dataa, datab, datac
    );
  end

always
  #10 clk = ~clk;
  
endmodule